Sunshine Lab: Power Supply Design Engineering & Pre-Cert R&D
Last Updated: September 7, 2026 · Reviewed by the Sunshine Electronics engineering team
If your procurement team needs to verify power supply design engineering depth before committing to a Custom OEM or Full ODM contract, Sunshine Electronics runs a real engineering test bench — Sunshine Lab — across China and Vietnam: Changzhou, China (est. 2003, 200+ workers, 25,000 sqm) and Vinh Phuc, Vietnam (est. 2018, 600+ workers, 12,000 sqm). The lab houses Chroma 8030 / 8020 auto-test rigs, ADSYS 7000 ICT, ST-516 AOI, Hioki-class Y8800 high-voltage insulation testers, TESEQ lightning testers for IEC 61000-4-5 surge immunity, LECROY + Rigol DS1072 oscilloscopes, and a Yokogawa automatic temperature recorder. The lab evaluates topology fit (silicon flyback, GaN-Si hybrid, full-GaN, two-switch forward, LLC resonant), runs pre-cert engineering review against UL 62368-1, FCC Part 15, and DOE Level VI, and catches the failure modes that fail at the cert lab — before they ship. 22+ years of switching power supply design (since 2003) for AT&T, DirecTV, Amphenol, and Vericom.
What Sunshine Lab Does
Sunshine Lab is the engineering test bench behind every Custom OEM and Full ODM build. It is not a marketing department, not an aspirational research lab — it is a working lab with a named instrument rack, an engineering review process, and a closed-loop failure-analysis pipeline. The lab runs six core activities, all of which feed your build:
Topology Evaluation
For every new build, the lab evaluates which switching topology fits — silicon flyback for low-W consumer adapters, GaN-Si hybrid flyback for mid-range laptop chargers, full-GaN flyback or LLC resonant for premium PD chargers, two-switch forward for industrial and desktop adapters, LLC resonant half-bridge for high-W ATX-class. Topology selection drives BOM cost, package size, and efficiency simultaneously.
GaN HEMT Component Qualification
The lab evaluates wide-bandgap devices from leading GaN vendors before they enter a production BOM. Sample-stage qualification covers RDS(on) at operating junction temperature, Coss vs gate-drive compatibility, package thermal resistance, and Qg/Coss figure of merit. Datasheet numbers are not the same as bench measurements.
Custom Transformer Design
For builds that need an off-catalog magnetic, the lab specs the transformer winding (turns ratio, leakage inductance, primary/secondary insulation), gapping (energy storage tuning for flyback), and core selection (ferrite material grade vs frequency vs core loss).
Pre-Cert Engineering Review
Before a design ships to UL Solutions, Intertek, Waltek, NTEK, CTI, or ICAS, the lab runs a five-phase pre-cert pathway. Failed cert submissions cost 4-8 weeks and 5-figure lab fees — the goal is to never submit a design that fails.
EMC Bench Simulation + Immunity Testing
The lab runs surge immunity per IEC 61000-4-5, fast-transient burst per IEC 61000-4-4, ESD per IEC 61000-4-2, and radiated emission pre-scans against FCC Part 15 Class B before the design goes to the cert lab.
Failure Analysis on Field Returns
RMAs come back to the lab for root-cause analysis. Every field failure mode gets traced to a design or BOM root cause, written into a corrective action, and folded into the next-generation reference design. This is how the topology library and approved-vendor list stay current.
Sunshine Lab — engineering review at the bench. Every Custom OEM and Full ODM build clears a five-phase pre-cert review before it ships to the cert lab.
The Test Rack: 12 Named Instruments at the Engineering Bench
The instruments below run validation on every Custom OEM and Full ODM build before it leaves Sunshine Lab. Each one is named because procurement audits look for specific tools — generic “calibrated test bench” claims do not survive due-diligence. Use this list when verifying that your supplier has the rack to back up the cert claim.
From our test engineering team
the specific reason we name the instruments is that procurement teams ask. Chroma 8030 functional-test results, Hioki Y8800 hipot logs, TESEQ surge-immunity test reports, and Yokogawa burn-in thermal records all leave a paper trail that can be audited against your incoming-inspection plan. We attach the test data to your Custom OEM build packet on request.
SMPS Topology Library: Sunshine Lab Reference Framework
Sunshine Lab evaluates topology fit per project. Every switch mode power supply build maps to one of these rows. SMPS design is the lab’s core competency — topology selection, EMC layout, and pre-cert engineering review on every Custom OEM and Full ODM project. The library below is the lab’s switching power supply reference framework, drawing on IEEE Power Electronics Society design conventions — every Custom OEM build maps to one of these rows. Topology selection is the BOM-cost vs size vs efficiency tradeoff that drives 60-70% of the design decision; the remaining 30-40% is component qualification, EMC layout, and cert engineering.
| Topology | Switching Frequency | Wattage Range | Efficiency | Common Use | Sunshine Builds? |
|---|---|---|---|---|---|
| Linear regulator | n/a (no switching) | <10W | 30-60% | Low-noise lab benchtop, audio | ❌ Different category |
| Flyback (silicon) | 50-150 kHz | 5-75W | 80-88% | Wall-plug adapters, SMB router PSUs | ✅ Standard line |
| Flyback (GaN-Si hybrid) | 200-500 kHz | 30-100W | 88-91% | Mid-range laptop chargers, mid-W adapters | ✅ Per project |
| Forward / two-switch forward | 100-300 kHz | 50-200W | 85-90% | Industrial, desktop adapters | ✅ Per project |
| Half-bridge | 100-500 kHz | 100-500W | 88-92% | Higher-W industrial, server PSU | ✅ Per project |
| LLC resonant half-bridge | 100 kHz – 1 MHz | 75-1000W | 92-95% | Premium laptop, high-W ATX, GaN topology | ✅ Per project |
| Full-GaN flyback / LLC | 500 kHz – 2 MHz | 65-240W | 92-95% | Premium PD chargers, GaN HEMT designs | ✅ Per project (see Computing & Office) |
The lab’s default selection logic: lowest-cost topology that hits the efficiency target with margin, highest-density topology that fits the housing, and proven-vendor BOM that has cleared UL 62368-1 in a previous Sunshine build. Custom topologies — full-GaN at 1.5 MHz+ for premium PD chargers, LLC resonant for high-W ATX-class — get evaluated when the BOM-cost trade clears.
Topology Deep-Dive: When Each Topology Fits
Each topology fits a specific BOM-cost / housing-density / efficiency tradeoff. The lab’s default selection logic: lowest-cost topology that hits the efficiency target with margin. Below: when each one fits.
Silicon Flyback
The default topology for the volume bulk of Sunshine's production (per TI Power Supply Design Notes) — wall-plug adapters, SMB router PSUs, low-W consumer adapters. The cost floor is here: silicon MOSFET, commodity flyback transformer, conventional electrolytic bulk cap. Efficiency tops out around 88% which clears DOE Level VI and EU Ecodesign Regulation 2019/1782 with margin for most product classes.
→ Desktop power adaptersGaN-Si Hybrid Flyback
The bridge topology (see ADI Power Pavilion) — silicon primary-side switch paired with GaN-Si hybrid for the synchronous rectifier, or vice versa. Pushes density without paying full GaN BOM cost. Common for mid-range laptop chargers and 65W-class PD adapters where housing space matters but the premium-tier BOM does not.
→ USB-C power adaptersFull-GaN Flyback / LLC
The premium-tier topology (per IEEE Power Electronics resources reference frameworks) — full GaN HEMT on both primary and secondary, switching frequency in the 1-2 MHz range, transformer size shrinks dramatically. Used for premium GaN chargers and PD 3.1 EPR builds with 28V / 36V / 48V output negotiation. Efficiency advantage is real (92-95%); the EMC layout penalty is also real.
→ GaN chargersTwo-Switch Forward
The industrial / desktop topology under IEC 62368-1 Standard — fault-tolerant, tolerates wider input voltage ranges, simpler magnetics than half-bridge. Used for industrial control adapters, desktop PC power, and applications where the low-W premium of LLC does not justify the BOM cost. Two-switch forward survives partial short conditions that a flyback would not.
LLC Resonant Half-Bridge
The high-W topology validated against ENERGY STAR EPS — premium laptop adapters in the 100W+ class, high-W ATX-class server PSUs, and any application where 92-95% efficiency targets need to be hit across the load range. LLC resonant achieves zero-voltage switching across the resonant frequency range — the efficiency ceiling lives there.
GaN HEMT Component Evaluation: Sunshine Lab's Qualification Process
GaN HEMT (Gallium Nitride High Electron Mobility Transistor) devices have moved from research-tier into production-tier topology over the last 5-7 years. The lab evaluates wide-bandgap devices from leading GaN HEMT vendors before any new device enters a production BOM — datasheet numbers are not the same as bench measurements, and the bench measurement is what survives field deployment. Sample-stage qualification covers four dimensions:
RDS(on) at operating junction temperature
Datasheet RDS(on) is typically quoted at 25°C. Real operating Tj in a GaN flyback at full load is 80-110°C. RDS(on) at 100°C is 1.4-1.8× the 25°C number for most GaN devices — that delta directly drives conduction loss and efficiency at full load. The lab measures RDS(on) on the actual device sample at the actual Tj.
Coss vs gate-drive compatibility
GaN devices have small Coss compared to silicon — good for switching loss, challenging for soft-start and dV/dt control. The gate driver has to be matched to the Coss; mismatch causes either insufficient turn-on speed (high switching loss) or excessive dV/dt (EMC penalty). The lab characterizes the actual gate-drive waveform on the bench.
Package thermal resistance
Most GaN HEMT devices ship in DFN / QFN-class packages with 1-3 K/W thermal resistance junction-to-case. Real heat-sinking in a sealed adapter housing pushes junction-to-ambient closer to 30-50 K/W. The lab measures the case temperature on the actual reference design under full-load burn-in to validate thermal margin.
Qg/Coss figure of merit
The headline GaN advantage (per TI Power Management reference). Lower Qg/Coss means lower switching loss at higher switching frequency, which is the design lever that lets full-GaN topologies hit 92-95% efficiency at 1-2 MHz. The lab benchmarks Qg/Coss against silicon equivalents for each new GaN sample to confirm the topology advantage holds in the actual operating point.
Sunshine Lab — component evaluation bench. New GaN HEMT samples clear RDS(on), Coss, thermal resistance, and Qg/Coss benchmarking before they enter a production BOM.
EMC Bench: Power Supply Design Layout & Surge Immunity
Pre-compliance testing on the bench is the single most reliable defense against cert lab slips. EMC failure at the cert lab is the most common reason a switching power supply design slips schedule. The lab\u2019s answer is to run EMC pre-scans on the bench before submitting to UL Solutions, Intertek, Waltek, NTEK, CTI, or ICAS. Pre-scan failures get fixed in-house in 1-2 days; cert lab failures cost 4-8 weeks plus re-submission fees.
PCB Layout Tradeoffs
Most EMC failures trace to PCB layout, not component selection. The lab reviews multi-layer ground plane integrity (no split planes under switching nodes), common-mode choke selection (common-mode impedance at the switching frequency), Y-capacitor selection (line-to-earth capacitance vs leakage current), and snubber design (RC snubber across the primary switch to damp ringing).
Switching Frequency vs EMC Penalty
Pushing the switching frequency from 100 kHz silicon to 1 MHz GaN gains efficiency and shrinks the transformer, but the EMC fundamental moves into the FCC Part 15 conducted-emission measurement band (150 kHz – 30 MHz). The lab compensates with tighter common-mode choke design, ferrite bead on the DC output cable, and Y-capacitor optimization. The frequency-vs-EMC tradeoff is real and has to be designed-in from PCB layout, not bolted-on.
Surge Immunity — IEC 61000-4-5 on TESEQ
Mains-line surge per IEC 61000-4-5 tests 2 kV common-mode and 1 kV differential-mode pulse injection on the AC input (including IEC AC power cord coupling paths) — simulating real-world lightning-induced transients on the mains. Always-on equipment (network gear, industrial controls) needs to survive these pulses without failing or losing data. The lab tests all designs on the TESEQ lightning tester before submission.
Fast-Transient Burst + ESD
The other two pre-scan protocols. Fast-transient burst (IEC 61000-4-4) simulates contactor switching noise on the mains. ESD (IEC 61000-4-2) simulates 4-8 kV human-body-model discharge to user-touch surfaces. Both are common cert lab failures and both get pre-scanned on the bench.
Radiated Emission Pre-Scan
The lab runs near-field radiated emission pre-scans with a probe at 30 MHz – 1 GHz to identify hot-spot frequencies before submitting to FCC Part 15 Class B compliance testing at the cert lab. Pre-scan misses get fixed by ferrite bead, common-mode choke, or PCB layout rework — never by a 'tighter cert margin' excuse.
Pre-Cert Engineering Review: Sunshine Lab's 5-Phase Pathway
Every Custom OEM and Full ODM design clears the lab’s five-phase pre-cert engineering review before it ships to the cert lab. The goal: never submit a design that fails. Failed cert submissions cost 4-8 weeks and 5-figure lab fees per re-submission, plus the schedule penalty for downstream production planning. The five phases catch the failures that matter, in the order they matter.
Spec Review
Input voltage range (universal 90-264 VAC vs region-specific), output voltage / current regulation tolerance (typically ±5% or ±2% for medical), ripple budget (120 mV pp consumer, 50 mV pp industrial), transient response (typically <5% deviation on 50% load step), efficiency target (DOE Level VI vs EU CoC Tier 2), cert pathway target (UL 62368-1 / IEC 62368-1 / UL 60601-1 / UL 61010-1), regional overlay set (PSE, KC, BIS, NOM).
BOM-vs-Cert Crosswalk
Every cert-impacting component (primary switch, transformer, opto-isolator, Y-cap, common-mode choke, output cap) gets pre-checked against UL Recognized Component lists, REACH SVHC database, and RoHS substance-restriction lists. A single non-Recognized component triggers a cert failure — the crosswalk catches it before the lab does.
EMC Simulation
PCB layout review for common-mode and differential-mode noise prediction. Common-mode current path (transformer interwinding capacitance to chassis to AC line), differential-mode current path (switching node ringing on the primary loop). Layout defects identified at this phase get fixed in PCB Rev B before tooling commits.
Thermal Modeling
Component dT calculation under full load, hot-spot identification (typically primary MOSFET, transformer, output rectifier, bulk cap), and derating verification against the operating temperature range. The lab cross-checks the Yokogawa burn-in thermal log against the model — model-vs-bench discrepancies of more than 10°C trigger a redesign, not a cert submission.
Bench Validation
Full set of 12+ named instruments — Chroma 8030 functional test, Hioki Y8800 hipot at 3 kV / 1s, ADSYS 7000 ICT, ST-516 AOI, TESEQ surge per IEC 61000-4-5, fully-automatic burn-in chamber bank, Yokogawa thermal log, ripple measurement on LECROY + Rigol DS1072 oscilloscopes. Designs that clear all five phases ship to the cert lab under IECEE CB Scheme recognition; designs that fail any phase loop back to engineering for rework before submission.
From our engineering team
the most common reason a design fails Phase 2 (BOM-vs-cert crosswalk) is a transformer or opto-isolator from a vendor that holds UL Recognition for a different cert standard than what your build targets. UL Recognition is scoped — a transformer recognized for UL 60950 may not carry over to UL 62368-1 without a re-evaluation. The lab maintains a per-vendor cross-cert recognition matrix and flags this at Phase 2 before tooling commits.
Common Pre-Cert Failure Modes Sunshine Lab Catches
The failure modes below are the ones the lab catches most often during the 5-phase review — the failures that would otherwise reach the cert lab and slip the schedule. They are not theoretical; every Sunshine Lab engineer has fixed each of these in a recent build. Roughly 80% of cert lab failures trace to one of these six modes, and all six are catchable on the bench.
DOE Level VI 25%-Load Efficiency Miss
Silicon flyback at 25% load typically falls 2-4 percentage points below full-load efficiency due to switching loss not scaling with conduction loss. DOE Level VI tests at 25%, 50%, 75%, and 100% load — the 25%-load number is where many silicon designs miss.
Switch to GaN-Si hybrid flyback OR add a burst-mode controller for low-load operation. The lab catches this at the thermal modeling phase by checking efficiency curve shape, not just full-load efficiency.
Cold-Start Over-Voltage Trip
Bulk capacitor inrush at AC turn-on combined with mistuned soft-start charges the bulk cap fast enough to push the primary-side over-voltage protection to trip. Common in designs with aggressive soft-start (for fast-startup spec) or insufficient inrush limiter (NTC thermistor sized wrong).
Re-tune soft-start time constant, resize NTC, or add active inrush limiting. The lab catches this on the variable-frequency power source by stepping AC turn-on across line-voltage range.
USB-IF Compliance Test Failure
ID resistor on the USB-C connector is the #1 source — wrong resistor value or wrong CC pin pull-up causes the host to mis-detect the device class. VBUS sequencing (VBUS-on before SS lanes, SS lanes before USB 2.0 lanes) is the #2 source. Advertised PDO mismatch is the #3 source.
Verify ID resistor at PCB-stuff phase, verify VBUS sequencing on the LECROY oscilloscope, run PDO advertising against a USB-IF compliance tester before submitting to USB-IF certification.
EMC Radiated Emission Spike at 30 MHz
The DC output cable acts as an antenna (per IPC-A-610 Class 2 harness routing rules) at the harmonics of the switching frequency. A 100 kHz switcher has a 30 MHz harmonic in the FCC Part 15 measurement band; a 1 MHz GaN switcher pushes the fundamental into the band.
Ferrite bead on DC output, common-mode choke at the secondary, or output-cable length restriction. The lab pre-scans on a near-field probe before submitting to FCC Part 15.
ESD Susceptibility ±8 kV Contact Discharge
Gate-drive node lacking series gate resistor or TVS diode allows ESD pulse to couple into the primary MOSFET gate, causing latchup or destruction. Common on first-pass GaN designs because GaN devices have lower gate-pulse tolerance than equivalent silicon (per ESD S20.20 handling controls).
4.7-22 ohm series gate resistor + bidirectional TVS clamp on the gate node.
IP65 Water Ingress at Gasket-Housing Interface
Outdoor IoT and industrial designs need IP65 (water-jet protection) per IEC 60529. Most failures trace to the gasket compression at the housing seam — either the gasket is thin enough to deform unevenly under housing-screw torque, or the seam geometry has a horizontal-running ridge that the gasket cannot conform to.
Switch to a recessed gasket channel + 1.5-2.0 mm gasket thickness. The lab tests on the IPX5 spray rig before shipping the design to industrial deployments.
From our test engineering team
the failure modes above are the ones we see across hundreds of pre-cert reviews. The pattern is consistent: ~80% of cert lab failures trace to one of these six failure modes, and all six are catchable on the bench with the named instruments above. The 5-phase pre-cert pathway exists specifically to catch them in-house before the cert lab catches them — pre-cert in-house costs 1-2 engineer-days; cert-lab failure costs 4-8 weeks and 5 figures.
Engineering Specialty Matchmaker: Lab Capability by Industry
Sunshine Lab’s engineering specialties map to specific industry verticals. The cards below match a lab capability to the industry that drives the most demand for it. Click through to the Industries page for vertical-specific spec detail.
Related Sunshine Capabilities
Sunshine Lab is the engineering test bench. The capabilities below are the surrounding production, quality, cert, and dual-factory infrastructure that takes a Lab-validated design to production volume. Engineering depth + production scale = a complete Custom OEM contract.
Sunshine Lab Engineering FAQ
What does Sunshine Lab actually do?
Sunshine Lab is the engineering test bench behind every Custom OEM and Full ODM build. It is not a marketing department or aspirational research lab — it is a working lab with a named 12-instrument rack (Chroma 8030, Hioki Y8800, ADSYS 7000 ICT, TESEQ lightning tester, LECROY + Rigol DS1072 oscilloscopes, Yokogawa thermal recorder, fully-automatic burn-in chamber, etc.) running six core activities: topology evaluation, GaN HEMT component qualification, custom transformer design, pre-cert engineering review, EMC bench testing, and failure analysis on field returns. The lab serves both the Changzhou and Vinh Phuc plants with identical equipment and process.
What's the difference between a linear and switching power supply?
A linear regulator drops voltage across a series-pass element (BJT or LDO MOSFET) — simple, low-noise, but 30-60% efficient. A switching power supply (SMPS) chops the input voltage at high frequency (50 kHz – 2 MHz), passes it through an inductor or transformer, and rectifies/filters the output — 80-95% efficient depending on topology. Sunshine builds switching power supplies almost exclusively (linear regulators are a different product category). The efficiency advantage is the reason: a 65W linear regulator wastes 30-40W as heat, requiring a heat sink and housing space; the equivalent switching design wastes 4-7W and fits in a wall-plug form factor.
What are the most common SMPS topologies and when does each apply?
The most common topologies for the wattage classes Sunshine builds: silicon flyback (5-75W, wall-plug adapters and SMB router PSUs), GaN-Si hybrid flyback (30-100W, mid-range laptop chargers and 65W PD adapters), full-GaN flyback / LLC (65-240W, premium PD chargers and USB PD 3.1 EPR builds), two-switch forward (50-200W, industrial and desktop adapters), and LLC resonant half-bridge (75-1000W, premium laptop adapters and high-W ATX-class server PSUs). Topology selection (see ADI Power Management reference framework) drives BOM cost, package size, and efficiency simultaneously, and Sunshine Lab evaluates the topology fit per project. See the topology library table above.
When should I choose silicon vs GaN HEMT in my switching power supply design?
Silicon is the right call for low-W consumer adapters (under ~30W), high-volume builds where the BOM-cost delta does not justify the efficiency gain, and applications where 88% efficiency clears DOE Level VI with margin. GaN HEMT is the right call for premium PD chargers (65-240W where housing density matters), high-switching-frequency designs (above 500 kHz where silicon switching loss becomes prohibitive), and applications where 92-95% efficiency is the spec. Sunshine Lab\u2019s default selection logic: lowest-cost topology that hits the efficiency target with margin. The lab does not push GaN where silicon clears the spec. See the Computing & Office Industries page for GaN-specific procurement detail.
What's Sunshine Lab's pre-cert engineering review process?
A five-phase pathway: (1) spec review, (2) BOM-vs-cert crosswalk, (3) EMC simulation, (4) thermal modeling, (5) bench validation on the full 12-instrument rack. The goal is to never submit a design that fails — a failed cert lab submission costs 4-8 weeks and 5-figure lab fees, plus the schedule penalty for downstream production planning. The lab catches roughly 80% of cert lab failures at Phase 2-4 before the design ships to UL Solutions, Intertek, Waltek, NTEK, CTI, or ICAS. See the Certifications & Compliance page for the per-product cert pathway breakdown.
How long does a switching power supply design cycle take from spec to first production?
Roughly 10-22 weeks total, with parallel paths: 4-8 weeks engineering review (Sunshine Lab, including pre-cert phases 1-5), 2-3 weeks tooling, 4-8 weeks cert lab submission and turnaround, 2-3 weeks first-production verification and pack-out. Specific timelines depend on cert pathway (medical-grade UL 60601-1 takes longer than UL 62368-1 ITE), tooling complexity (custom transformer adds 1-2 weeks), and any regional overlay certs. For service-tier-specific lead times and contract terms, see the OEM/ODM Manufacturing page.
Can Sunshine Lab evaluate a custom GaN HEMT topology for my OEM build?
Yes. The lab evaluates new GaN HEMT devices and topologies on a per-project basis — RDS(on) at operating Tj, Coss vs gate-drive compatibility, package thermal resistance, and Qg/Coss benchmarking against silicon equivalents. Lead time for a new topology evaluation is typically 2-4 weeks, depending on sample availability and the depth of the topology change. For custom-tier and ODM-tier builds where a non-standard topology is in scope, talk to Sunshine Lab Engineering at the spec-review stage — earlier-stage involvement reduces total design-cycle time.
Where does Sunshine Lab fit in the OEM contract — pre-RFQ, post-RFQ, or both?
Both. Pre-RFQ: procurement teams reference Sunshine Lab as part of supplier due-diligence — verifying engineering depth before committing to a Custom OEM or Full ODM contract. Post-RFQ: Sunshine Lab runs the 5-phase pre-cert engineering review on every awarded build, plus the closed-loop failure analysis on field returns. The Lab is embedded in the OEM contract lifecycle, not a separate service. The contract framework lives on the OEM/ODM Manufacturing page; Sunshine Lab is what makes the Custom OEM and Full ODM tiers credible at delivery.
Talk to Sunshine Lab Engineering in 24 Hours
Talk to Sunshine Lab Engineering about your switching power supply design — topology fit, GaN evaluation, pre-cert review pathway, or EMC layout question. 22+ years of switching power supply design (since 2003) for AT&T, DirecTV, Amphenol, and Vericom; engineering test bench at both Changzhou, China and Vinh Phuc, Vietnam with identical 12-instrument racks. RFQ response in 24 hours.